| Description | Presentation | Lab Files | Video | Note |
Module 1 |
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| VHDL capture to hardware (basic combinational logic system) |  |
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| 1.1 » Introduction, Hardware Demonstration, Project Files |  |
11 mins | ||
| 1.2 » Invoking ISE tools, creating ISE Project, Viewing RTL and Technology Schematic | |
11 mins | ||
| 1.3 » VHDL Testbench creation and VHDL Simulation. Creation of simulator macro files. Viewing Placed & Routed Design |
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11 mins | ||
| 1.4 » Structural VHDL | |
6 mins | ||
| 1.5 » Top (FPGA) Level VHDL Simulation | |
10 mins | ||
| 1.6 » VHDL Synthesis & FPGA H/W Implementation. Viewing P&R Design in FPGA. | |
16 mins | ||
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| VHDL origins, applications and usage | |
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| VHDL keyword grid | |
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Module 2 |
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| VHDL capture to hardware for synchronous (register-based) system | |
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| 2.1 » VHDL Capture to Hardware Implementation for synchronous / register-based systems | |
4 mins | ||
| 2.2 » Register-based system block diagram. Project files. Xilnx ISE Project creation | |
4 mins | ||
| 2.3 » D Flip Flop VHDL Model. Synthesising VHDL and Viewing RTL Schematic. | |
7 mins | ||
| 2.4 » DFF VHDL testbench and simulation | |
8 mins | ||
| 2.5 » FPGA Top level VHDL model. FPGA Top level simulation / VHDL testbench | |
11 mins | ||
| 2.6 » FPGA Implementation, FPGA pinout, generating FPGA configuration bitstream. | |
10 mins | ||
| 2.7 » VHDL coding recommendations | |
4 mins | ||
Module 3 |
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| VHDL for 'above gate-level' combinational model description | |
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| 3.1 » Introduction, Overview of application, overview of laboratory files | |
6 mins | ||
| 3.2 » Multiplexer function, Entity declaration, MUX using if-then-else, VHDL and concurrency | |
8 mins | ||
| 3.3 » if-then-else statement syntax, inferring latches (often incorrectly) and flip flops | |
6 mins | ||
| 3.4 » Mux using Case & Concurrent statements | |
7 mins | ||
| 3.5 » Simulation of muxAndDecEx1, sensitivity list rules, top level VHDL models and simulation | |
8 mins | ||
| 3.6 » FPGA hardware implementation and demonstration of hardware operation | |
4 mins | ||
Module 4 |
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| VHDL for efficient testbenches | |
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| 4.1 » Applying TB stimulus using: For Loop, Stimulus Array, Text Stimulus File | |
13 mins | ||